AMD's next-gen Ryzen 9000 processors are expected to launch later this year. The Zen 5 core architecture has been upgraded on all fronts, including the frontend, backend, memory sub-system, and cache. The branch predictor of Zen 5 can access the BTB without any penalties. The decoder looks untouched, but the dispatch queue has been widened from 6 to 8 micro-ops with support for op fusion. Zen 5 strengthens AMD’s already formidable Integer Execution. AMD’s Ryzen 8000 processors will use an upgraded core interconnect known as Ladder L3 Fabric. The core counts and higher-level cache buffers are expected to remain unchanged.
The Zen 5 CPUs will likely assume the Ryzen 9000 nomenclature. The Ryzen 8000 CPUs should feature up to 16 cores across two CCDs, each with 32MB of L3 cache. The L2 cache will remain 1MB per core or 16MB for the entire CPU. The core clocks should be on par or higher than the Ryzen 7000 parts.
AMD's next-gen Ryzen 9000 processors are slated to launch later this year. The Zen 5 core architecture has been upgraded on all fronts, including the frontend, backend, memory sub-system, and cache. The branch predictor of Zen 5 can access the BTB without any penalties. The decoder looks untouched, but the dispatch queue has been widened from 6 to 8 micro-ops with support for op fusion. Zen 5 strengthens AMD’s already formidable Integer Execution. AMD’s Ryzen 8000 processors will use an upgraded core interconnect known as Ladder L3 Fabric. The core counts and higher-level cache buffers are expected to remain unchanged.
In an out-of-order CPU, the branch predictor is one of the most crucial components. It directly affects the utilization of the various ALUs by dictating the pipeline’s flow. It affects stalls and flushes (in the case of incorrect branches) that are highly detrimental to IPC. Zen 5’s branch predictor executes “Zero bubble” conditional branches.
This means that the branch predictor of Zen 5 can access the BTB without any penalties (mostly one RR) or bubbles. Zen 5 also upgrades the capacity and accuracy of its Branch Target Buffer, which is crucial in conditional indirect branches.
Interestingly, the decoder looks untouched, but the dispatch queue has been widened from 6 to 8 micro-ops with support for op fusion. This allows two micro-ops from the same instruction to be treated as one at some points in the pipeline, doubling the effective throughput.
The backend has also gotten ample attention. Zen 5 strengthens AMD’s already formidable Integer Execution. The ALU count has been increased from 4 to 6, paired with a larger Scheduler. On the Vector/FP Side, 512-bit wide FP units have been added to improve AVX512 performance. The wider ALU may be limited to the Epyc offerings, leaving it fused on the Ryzen 8000 CPUs. The Memory Sub-system hasn’t been ignored either. Zen 5 can do 4 loads or 2 stores, up from 3 loads per cycle on Zen 4.
AMD’s Ryzen 8000 processors will use an upgraded core interconnect known as Ladder L3 Fabric (originally leaked by AdoredTV). This is related to the 3rd Gen Infinity Fabric, which will act as the die interconnects for AMD’s next generation of chiplet products.
The core counts and higher-level cache buffers are expected to remain unchanged. The Ryzen 8000 CPUs should feature up to 16 cores across two CCDs, each with 32MB of L3 cache. The L2 cache will remain 1MB per core or 16MB for the entire CPU. The core clocks should be on par or higher than the Ryzen 7000 parts. After all, the 4nm (N4) node is a customized variant of the 5nm process powering Zen 4.
The Ryzen 8000 CPUs are expected to land in mid to late 2024. You can expect a summer or fall launch.
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